FIG. 1 is an exploded perspective view showing a conventional ATE system 100, which represents a typical system utilized to test packaged integrated circuits (ICs) prior to sale to an end user. Conventional ATE system 100 includes an IC test signal generator (device tester) 110 (partially shown), a load board 120, a docking plate 130, and an automated handler (not shown) for mounting IC DUTs onto load board 120. Briefly described, the handler associated with ATE system 100 moves an IC DUT from a shipping tray (not shown) onto a test socket 127 that is mounted on load board 120. Alternatively, this process may be done by hand (i.e., manually). Testing is then carried out by transmitting electrical signals from device tester 110 to an IC DUT through test socket 127, and processing test data returned from the IC DUT in response to the applied test signals. This testing process is typically used to identify non-functional ICs.
Referring to the lower portion of FIG. 1, device tester 110 is an expensive piece of computing equipment that includes a base unit (partially shown) having a test surface 112 located at one end. Extending from test surface 112 are a first platform 140 having a first group 113 of compressible test (“pogo”) pins arranged in a first column, and a second platform 150 having a second group 115 of compressible test pins arranged in a second column that is parallel to the first column such that a central channel 117 is defined between first and second platforms 140 and 150. A blow-up of an example set of pogo pins is shown as 113-1. Not shown in order to simplify the description are the seals which surround the compressible test pins 113 and 115 (see for example, seals 142 and 152 of FIG. 5). Also extending from test surface 112 are several connection bolts 119 that are used to secure load board 120 to device tester 110. An example of conventional device testers that are consistent with device tester 110 is the Integra J750 Test Family, which is produced by Teradyne, Inc. of Boston Mass., USA.
Located above device tester 110 is load board 120, which is a printed circuit board (PCB) having a lower surface 121 facing test surface 112 and an upper surface 122 facing away from test surface 112, and includes a first plurality of test contacts 123, a second plurality of test contacts 125, and one or more test sockets 127. First test contacts 123 are arranged in a first column, and each test contact includes a contact pad located on lower surface 121 such that each contact pad abuts the tip of a corresponding compressible pin of first group 113 when load board 120 is mounted onto device tester 110. Similarly, contact pads of second test contacts 125 are arranged on lower surface 121 in a second column such that each test contact abuts the tip of a corresponding compressible pin of second group 115. Test sockets 127 are mounted on upper surface 122, and include pins or other contact structures that are connected to corresponding first and second test contacts 123 and 125 by conductive traces (wires) 128, which are formed in accordance with known practices. Finally, load board 120 is secured to device tester 110 using connectors 129 that receive the ends of bolts 119 and hold load board 120 such that the compressible pins of first group 113 are firmly pressed against the contact pads of first test contacts 123, and such that the compressible pins of second group 115 are firmly pressed against the contact pads of second test contacts 125.
Shown above load board 120 is docking plate 130, which is a rigid (e.g., aluminum) structure that is fixed (e.g., screwed) to upper surface 122 of load board 120, and includes openings 135 that mount over test sockets 127.
FIG. 2 is a cross-sectional side view showing conventional ATE system 100 with docking plate 130 mounted on load board 120, and load board 120 fastened to device tester 110. Note that compressible test pins of each group 113 and 115 are electrically connected to the DUT via corresponding conductive traces 128, and receive test signals from a central processing unit (CPU) 210. As indicated in the lower portion of FIG. 2, compressible pin groups 113 and 115 are mounted on a support plate 220 that has sufficient strength to resist the downward force from the compressible pins of groups 113 and 115 when load board is fastened onto the ends of bolts 119. As indicated previously, the seals surrounding compressible pin groups 113 and 115 are not shown in order to simplify the explanation.
As indicated at the top of FIG. 2, during testing, docking plate 130 functions to prevent bending of load board 120, which is subjected to a downward force P that is needed to press a DUT against test socket 127. Downward force P is used to provide the necessary connection between the contact structures of test socket 127 and contact structures (e.g., solder balls or bumps) formed on a lower surface of the DUT.
Low-temperature semiconductor device testing is often used to verify the conformance of a semiconductor device such as an IC with military specifications. During low-temperature testing, semiconductor devices are placed in a special low-temperature box containing a cool dry environment maintained at a temperature in the range of, e.g., 0° C. to −58° C., and a handler that moves the cooled semiconductor devices between a loading tray and a test socket that is coupled to a device tester.
FIG. 3 is an exploded perspective view and a simplified cross-sectional side view showing a portion of a conventional low-temperature testing arrangement 300 that utilizes test system 100 (described above). The conventional low-temperature testing arrangement 300 generally includes device tester 110, a low-temperature handler system 350, and load board 120, which connect between device tester 110 and handler system 350 during low-temperature testing procedures. Low-temperature handler system 350 includes an insulated box 352 connected to a cooling system (not shown), and a device handling mechanism (handler) 355 mounted inside of insulated box 352. An opening 357 is provided in a side wall of insulated box 352 through which test sockets 127 of handler board 120 are exposed to the cool dry environment maintained inside insulated box 352. Device handling mechanism 355 (partially shown) is an expensive precise robot including an arm for moving a DUT from a storage location (e.g., a shipping tray) to the test socket 127 during test procedures. The storage location is also inside of insulated box 352 so that the DUTs are maintained at a desired low temperature throughout the test procedures. Conventional systems meeting the description of low-temperature handler system 350 are produced, for example, by Delta Design of San Diego, Calif., USA.
A major problem associated with conventional low-temperature testing arrangement 300 is that, during low temperature testing, the low temperature of the DUT can cause condensation to form on the back surface 121 of load board 120. The potential for condensation is particularly high on the back surface 121 of load board 120 opposite test sockets 127 because of the cold temperatures conducted along contact structures 128 (see FIG. 2) from the cooled DUT. This condensation can cause a short circuit between any traces 128 or related contact structures that are exposed on back surface 121, thereby producing erroneous test signals.
What is needed is a structure for the low-temperature testing arrangements described above that reduces condensation during low temperature testing.